1. Field of the Invention
The present invention relates generally to microprocessors and, more specifically, to a method and system to combine multiple register units within a microprocessor, such as, for example, a digital signal processor.
2. Background
Typically, computer systems include one or more microprocessor devices, each microprocessor device being configured to perform operations on values stored within a memory of the computer system and to manage the overall operation of the computer system. These computer systems may also include various multimedia devices, such as, for example, sound cards and/or video cards, each multimedia device further including one or more processors, such as, for example, digital signal processors (DSPs), which perform complex mathematical computations within each respective multimedia device.
A digital signal processor (DSP) typically includes hardware execution units specifically configured to perform such mathematical calculations, such as, or example, one or more arithmetic logic units (ALU), one or more multiply-and-accumulate units (MAC), and other functional units configured to perform operations specified by a set of instructions within the DSP. Such operations may include, for example, arithmetic operations, logical operations, and other data processing operations, each being defined by an associated set of instructions.
Generally, the execution units within the DSP read data and operands from a register file coupled to the memory and to the execution units, perform the instruction operations, and store the results into the register file. The register file includes multiple register units, each register unit being accessible as a single register or as aligned pairs of two adjacent register units. However, certain specific operations, such as, for example, operations to add or subtract data, require data from separate register units within the register file to be properly aligned for execution of the instructions. Thus, what is needed is a method and system to combine multiple non-adjacent register units within a DSP during execution of a single instruction in order to enable proper alignment of data stored within such register units.